1. Field of the Invention
The present invention relates to a frequency multiplier and, more particularly, to a frequency multiplier capable of multiplying the frequency of an input clock signal and adjusting the duty cycle of the input clock signal.
2. Description of the Related Art
Frequency multipliers are often used to multiply the frequency of an input clock signal for use with synchronous semiconductor memory devices. Since the frequency of the input clock signal is directly related to the operating speed of elements of the synchronous semiconductor memory devices, it is advantageous to be able to convert a low frequency clock signal into a high frequency clock signal.
In general, the frequency multiplier includes a delay circuit and an XOR gate. The delay circuit delays the input clock signal by a time delay and outputs the delayed clock signal. The XOR gate performs an XOR operation using the clock signal and the delayed clock signal as inputs, and outputs a clock signal with a multiplied frequency.
FIG. 1 is a timing diagram for explaining the conventional procedure for doubling the frequency of an input clock signal to produce an output clock signal having a doubled.
Referring to FIG. 1, after the delay circuit (not shown) of the frequency multiplier delays an input clock signal CLK by a predetermined time delay and outputs a delayed clock signal CLKD, an XOR gate (not shown) of the frequency multiplier performs an XOR operation on the input clock signal CLK and the delay clock signal CLKD. This results in an output clock signal CLKX2 with a frequency twice that of the input clock signal CLK. In this manner, frequency multipliers can be used to multiply the frequency of an input clock signal CLK by a factor of two or more.
The duty cycle of a clock signal is one of the significant factors in operation of a synchronous semiconductor memory device with a high operating speed, i.e., operating in synchronization with a high frequency clock signal. In particular, with the introduction of double data rate (DDR) semiconductor memory devices, an accurate duty cycle of a clock signal becomes a key operation factor of such a semiconductor memory device.
As shown in FIG. 1, since the output clock signal CLKX2 is generated by performing the XOR operation on the input clock signal CLK and the delayed clock signal CLKD, the accurate duty cycle of the output clock signal CLKX2 is subject to the delayed clock signal CLKD. In other words, if the delayed clock signal CLKD is generated by delaying the input clock signal CLK by a time delay equal to a quarter cycle of the input clock signal CLK, the duty cycle of the output clock signal CLKX2 equals 50%. As such, the duty cycle of the output clock signal CLKX2 is obtained based on a phase difference between the input clock signal CLK and the delayed clock signal CLKD.